1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to the structure of a semiconductor memory device suitable for fabrication of a system device combining a memory circuit and a logic circuit.
2. Description of the Prior Art
In recent years, a system requiring parallel processing of mass data such as video data processing is increasingly employed.
Such a system employs a synchronous DRAM (hereinafter referred to as SDRAM) operating in synchronization with a clock signal for implementing quick access to a dynamic random access memory (hereinafter referred to as DRAM) or the like employed as a main memory following improvement in operating speed of a microprocessor (hereinafter referred to as MPU).
Such an SDRAM or the like employs a bank structure splitting a memory cell array into banks capable of operating independently of each other, in order to enable operations at a higher speed. In other words, the operations of each bank are independently controlled as to a row-system operation and a column-system operation. Quicker access is implemented by interleave-operating such banks and reducing a precharge time or the like.
In recent years, however, a DRAM/logic circuit hybrid chip, for example, has been developed by integrating a memory circuit and a logic circuit on a single chip, in order to attain a more advanced multi-function structure, improvement of the data processing speed and the like. In this case, the width of a data bus (the number of bits of simultaneously transferred data) transferring data between the memory circuit such as a DRAM and the logic circuit integrated on the single chip tends to increase for performing high-speed processing.
While high-speed processing can be implemented by increasing the width of an internal data bus on the chip, flexible manufacturing may be required depending on the system. In this case, the aforementioned structure of the DRAM/logic circuit hybrid chip results in the following problem:
The memory capacity required to the memory circuit and the word structure (the bit number of one word or the like) for transmitting/receiving data to/from the logic circuit vary with the performance required to the system or the like. If designing the circuits on the single chip for each system in response to the specifications when fabricating such a semiconductor device, therefore, a long term is disadvantageously required for product development.
In order to solve this problem, Japanese Patent Laying-Open No. 10-111864 (1998), for example, discloses a technique of connecting a RAM board and an MPU board serving as LSI cores oppositely to each other through a bonding technique for a semiconductor chip thereby fabricating a system formed by a logic circuit and a memory circuit as an integral device, in order to reduce the term for developing a semiconductor integrated circuit device while improving the performance of the circuits and reducing the cost.
In this technique, however, pads for attaining electrical connection must be formed on each of the boards oppositely bonded to each other with correct registration, leading to limitation in degree of freedom in circuit design of both the RAM board and the MPU board.
On the other hand, input/output lines (pairs of I/O lines) reading data from memory cells and transmitting the read data to an interface circuit are generally layered in view of improvement of the operating speed or the like. In order to transmit data read from a memory cell through any of the layered pairs of I/O lines, a gate circuit is provided for selectively connecting a pair of bit lines connected with the memory cell selected in reading with the pair of I/O lines transmitting the data. The number of elements of such a gate circuit tends to increase in a multi-bank memory cell array.
In order to input/output data with the aforementioned large data bus width, in particular, it is necessary to increase the number of pairs of I/O lines capable of operating independently of each other, leading to increase of the number of the aforementioned gate circuits and the number of elements forming the same.